Receivers for pulses of different widths

ABSTRACT

A data transmission system for transmitting data and subsidiary information by means of pulses of different widths corresponding to a multiple of a signal propagation time delay of a NAND gate. The system makes it possible to simplify the construction of the data transmission device to a considerable degree and at the same time to transmit data at a high speed, and includes a variety of circuits for generation and demodulation of the pulses.

This is a division of application Ser. No. 459,718 filed Apr. 10, 1974 now U.S. Pat. No. 3,993,945

BACKGROUND OF THE INVENTION Field of the Invention

This invention relates to an electric communication system, and more particularly to a data transmission system particularly suitable for use in the transfer of date between peripheral equipment and a computer or between two computers.

DESCRIPTION OF PRIOR ART

In transferring data between two computers, it has been the usual practice to provide two lines between the computers for sending clock signals on one line and transferring data on the other line in terms of binary data signals of "1" and "0" which are expressed by the presence or absence of a pulse signal. The known data transmission systems of this nature are disadvantageous in that they require two transmission lines and use a unipoler pulse which necessitate use of a particular combination of a number of "1" and "0" pulses for forming a subsidiary signal such as a message start signal or the like, resulting in prohibitive complication of the circuit. On the other hand, the known asynchronous transmission systems which use a single line also require use of a complicated pulse waveform for the subsidiary signal and therefore of complicated circuit arrangement.

SUMMARY OF THE INVENTION

It is therefore an important object of the present invention to provide an electric communication system which requires only a single communication line, which allows use of a pulse of a simple waveform, and which is capable of data transmission at a high rate.

It is another object of the present invention to provide a pulse generator circuit and a demodulation circuit suitable for use in an electric communication system for generating and detecting a width-modulated pulse.

A further object of the present invention is to provide a pulse width modulator and demodulator for data transmission, which are simple in construction, low in production cost and capable of high speed data transmission.

With the above objects in view, according to the present invention, the transmission signals are modulated in width by means of a NAND gate. The modulation of the pulse width is attained by the inherent logic function of the NAND gate and by the time delay of the NAND gate whch is generally called signal propagation delay or gate time.

When a pulse passes through an IC (integrated circuit) NAND gate, it usually takes a certain period of time in the order of 6 to 7 nano-seconds. This is generally called propagation delay or gate time. For example, with a NAND gate having two input terminals, if a signal "1" is supplied to both of the two input terminals, the output is "0. " If one of the input terminals is supplied with a signal "0," there will be obtained an output of "1." However, even if the signal to one of the input terminals is changed from "1" to "0", the output remains "0" during the gate time gt and becomes "1" only after lapse of the gate time gt.

In this connection, if a plural number (n) of NAND gates are connected in series, the first NAND gate assumes a transient or error state upon change of its input signal until termination of the gate time gt. When gt < t < 2gt where t is a time lapse after change of the input signal of the first NAND gate, the first NAND gate is in a normal state but the second NAND gate is in a transient or error state. Similarly, when (n - 1) gt<t<ngt, a NAND gate in the n <1 position and all the preceeding NAND gates are in normal state but a NAND gate in the n position is in a transient or error state. In this manner, the NAND gates successively assume a transient or error state as time lapses.

Under these circumstances, if the gate connection is effected in such a manner as to supply the input signal of the first NAND gate also to the fourth NAND gate, output pulses with a width of 3gt will appear at the output terminals of the fourth and the succeeding NAND gates. Likewise, if the input signal of the first NAND gate is supplied also to an input terminal of a sixth NAND gate, an output pulse having a width of 5gt will appear at the output terminals of the sixth and succeeding NAND gates. In this manner, by connecting an input of the first NAND gate to an input terminal of a NAND gate in a 2m position (where m is a positive integer), there will be produced a pulse having a width of (2m - 1)gt at the output terminals of NAND gates in the 2m and succeeding positions. In this instance, there are always an even number of NAND gates expressed by (2m - 2) = 2(m - 1) between the first NAND gate and the 2mth NAND gate. In this manner, with a series connection of a number of NAND gates, it is possible to obtain quite easily a pulse having a width corresponding to the gate time gt as multiplied by an odd number. In this instance, if there are odd number of NAND gates between the first and n-th NAND gates, no pulses will be obtained from any one of the NAND gates even if the input signal of the first NAND gate is fed to an input terminal of a n-th NAND gate.

The present invention is based on these discoveries and contemplates to effect pulse width modulation and pulse demodulation with use of the logic functions and gate time characteristics of the NAND gates.

According to the present invention, the data signals "0" and "1" are transmitted, for example, in terms of pulses having 3 and 5 gate time widths, respectively, while a start signal is transmitted in the form of a pulse having a 7 gate time width. The receiver can easily demodulate these signals into data signals "0" and "1" and a start signal. As no synchronization is required, there is not need for transmission of a clock signal with would necessitate the provision of an additional transmission line. Furthermore, owing to absence of complicated internal processing, a high rate data transmission is possible.

In addition to the foregoing advantages, the gate circuit combination allows easy detection of a pulse waveform edge and can provide detection circuitry which is far simpler than the known counterparts using a differential circuit and which is small in detection delay and relatively free from influences of noises. The width-modulated pulse can easily be detected or demodulated with use of a combination of the just-mentioned pulse waveform edge detector and a delay line circuit.

In the present invention, a series of a number of pulses with the different widths are sorted with use of a variety of detection circuits each comprising a pulse waveform edge detector and a delay line circuit. This demodulation system is capable of discriminating and detecting pulses of specific waveforms which are used for a variety of codes.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the invention will become apparent from the following description of preferred embodiments of the invention and the appended claims, taken in conjunction with the accompanying drawings, wherein:

FIG. 1a is a circuit diagram showing a number of NAND gates connected in series and employed for explaining operations by the NAND gates;

FIG. 1b is a diagram showing a particular NAND gate connection and employed for explaining the principles underlying the concept of the present invention;

FIG. 1c is a view similar to FIG. 1b;

FIGS. 1d and 2 are circuit diagrams of a pulse waveform generator for producing a width-modulated pulse;

FIG. 3 is a circuit diagram of a transmitter employed in the data transmission system of the present invention;

FIG. 4 is a diagram showing a modification of the circuit as shown in FIG. 1;

FIG. 5 is a diagram of various pulse waveforms employed for explaining operations of the circuit arrangement shown in FIG. 4;

FIG. 6 is a circuit diagram of a receiver employed in the data transmission system of the invention;

FIG. 7 is a block diagram of a pulse waveform front edge detector;

FIG. 8 is a block diagram of a pulse waveform rear edge detector;

FIG. 9a is a block diagram showing one particular example of the front edge detector shown in FIG. 7;

FIG. 9b is a block diagram showing one particular example of the pulse rear edge detector shown in FIG. 8.

FIG. 10 is a block diagram of a circuit for detecting pulses of a predetermined width;

FIG. 11 is a graphical illustration explanatory of the operations of the circuit shown in FIG. 10;

FIG. 12 and 13 are circuit diagrams of a width-modulated pulse demodulator according to the present invention;

FIG. 14 is a circuit diagram showing a particular example of the demodulator shown in FIG. 12;

FIG. 15 is a diagram showing particular examples of waveforms of width-modulated pulses;

FIG. 16 is a circuit diagram for producing width-modulated pulses as shown in FIG. 15;

FIG. 17 is a graphical illustration of pulses of some specific waveforms; and

FIG. 18 is a circuit diagram of a demodulator for the pulses of the specific waveforms as shown in FIG. 17.

DETAILED DESCRIPTION OF THE INVENTION:

FIG. 1a is employed for explaining general operations of NAND gates N₁ to N₅ which are connected in series, wherein if a signal "0" is fed to the input terminal 1, a signal "1" appears at the output terminal 2, with a signal "0" at the output terminals 3 and 5 and a signal "1" at the output terminals 4 and 6. On the other hand, if the signal at the input terminal 1 is "1," the signal at the output terminals 2, 4 and 6 is "0" while the signal at the output terminals 3 and 5 is "1." In this manner, the circuit of FIG. 1a operates according to the inherent theories of the NAND gate in its normal state. However, a detailed study will reveal that the signals at the respective output terminals change as shown in Table 1a below since each NAND gate has a transient time or a gate time of about 6 to 7 nano-seconds.

                  TABLE 1a                                                         ______________________________________                                         Terminals                                                                      Time       1○                                                                            2○                                                                            3○                                                                          4○                                                                          5○                                                                          6○                                   ______________________________________                                         A          0     1     0   1   0   1   ←Initial state                     t.sub.0    1     1     0   1   0   1                                           t.sub.1    1     0     0   1   0   1                                           t.sub.2    1     0     1   1   0   1                                           t.sub.3    1     0     1   0   0   1                                           t.sub.4    1     0     1   0   1   1                                           t.sub.5    1     0     1   0   1   0   ←Normal state                      ______________________________________                                          *    : Error state                                                             t.sub.0 : A time point when the signal at input terminal 1○ change      from "0" to "1".                                                               t.sub.1 = t.sub.0 + gt (gt: gate time)                                         t.sub.2 = t.sub.1 + gt                                                         t.sub.3 = t.sub.2 + gt                                                         t.sub.4 = t.sub.3 + gt                                                         t.sub.5 = t.sub.4 + gt                                                         t.sub.i  = t.sub.i-1 + gt                                                

More particularly, even if the signal at the input terminal 1 is changed from "0" to "1," the NAND gate N₁ keeps producing an output of "1" during the gate time gt and thus is in an error state, producing an output of "0" only after lapse of the gate time gt. With gt<t<2gt where t is a time lapse after the signal at the input terminal 1 has changed from "0" to "1," the NAND gate N₂ is in an error state and a normal output of "0" is produced at the output terminal 6 only after a lapse of 5gt (number of NAND gates × gate time (gt)).

Referring to FIG. 1b which shows a particular NAND gate connection for explaining the principles underlying the concept of the present invention, the NAND gates N₁ to N₈ are connected in series and connection is made such that the input signal of the first NAND gate N₁ is fed to the fourth NAND gate N₄. In this circuit arrangement, the input terminal L₁ of the fourth NAND gate N₄ is always fed with a signal of the level same as the input terminal 1, the respective output signals assuming the levels as shown in Table 1b below. Row A is the initial state. Row B indicates the state when connection L₁ is made between 1 and the other input to N₅ and with the signal at terminal 1 at "0." Then at t₀ the signal at 1 is changed from "0" to "1."

                  Table 1b                                                         ______________________________________                                         Terminal                                                                       Time    1○                                                                            2○                                                                            3○                                                                          4○                                                                          5○                                                                          6○                                                                          7○                                                                          8○                                                                          9○                          ______________________________________                                         A       0     1     0   1   0   1   0   1   0   ← Initial                 B       0     1     0   1   1   0   1   0   1     state                        t.sub.0 1     1     0   1   1   0   1   0   1                                  t.sub.1 1     0     0   1   0   0   1   0   1                                  t.sub.2 1     0     1   1   0   1   1   0   1                                  t.sub.3 1     0     1   0   0   1   0   0   1                                  t.sub.4 1     0     1   0   1   1   0   1   1                                  t.sub.5 1     0     1   0   1   0   0   1   0                                  t.sub.6 1     0     1   0   1   0   1   1   0                                  t.sub.7 1     0     1   0   1   0   1   0   0                                  t.sub.8 1     0     1   0   1   0   1   0   1   ←Normal                   t.sub.9 1     0     1   0   1   0   1   0   1   ↓state                  ______________________________________                                         *   : Error state                                                              t.sub.0 : A time point when the signal at input terminal 1○             changes from "0" to "1".                                                       t.sub.1 = t.sub.0 + gt (gt: gate time)                                          ##STR1##                                                                         : Pulse (width = 3gt)                                                  

As will be seen from Table 1b, by connecting the signal at the input terminal of the first NAND GATE N₁ to the input terminal of the fourth NAND gate N₄, a pulse with a width of 3gt is obtained at the output terminals of NAND gate N₄ to N₈. Similarly, if the input of the first NAND gate is connected to an input terminal of a NAND gate N_(2m) in a 2m-th position (where m is a positive integer), there will be obtained a pulse having a width of (2m -1) gt at the output terminals of the NAND gates in the 2m-th and succeeding positions.

However, if the input of the first NAND gate N₁ is connected to a NAND gate N_(2m-1) in an odd number position, there will be obtained no pulses at the output terminals of the respective NAND gates, as shown in FIG. 1c where the input of the first NAND gate N₁ is connected to the third NAND gate N₃. In this instance, the levels of the signals at the output terminals of the respective NAND gates are as shown in Table 1c below. A is the initial state. B is the state when the input from 1 is connected to one of the inputs to gate N₃.

                  TABLE 1c                                                         ______________________________________                                         Terminal                                                                       Time    1○                                                                            2○                                                                            3○                                                                          4○                                                                          5○                                                                          6○                                                                          7○                                                                          8○                                                                          9○                          ______________________________________                                         A       0     1     0   1   0   1   0   1   0   ←Initial                  B       0     1     0   1   0   1   0   1   0     state                        t.sub.0 1     1     0   1   0   1   0   1   0                                  t.sub.1 1     0     0   1   0   1   0   1   0                                  t.sub.2 1     0     1   1   0   1   0   1   0                                  t.sub.3 1     0     1   0   0   1   0   1   0                                  t.sub.4 1     0     1   0   1   1   0   1   0                                  t.sub.5 1     0     1   0   1   0   0   1   0                                  t.sub.6 1     0     1   0   1   0   1   1   0                                  t.sub.7 1     0     1   0   1   0   1   0   0                                  t.sub.8 1     0     1   0   1   0   1   0   1   ←Normal                                                                   ↓state                  t.sub.9 1     0     1   0   1   0   1   0   1                                  ______________________________________                                            : Error state                                                               t.sub.0 : A time point when the signal at input terminal 1○             changes from "0" to "1".                                                       t.sub.1 = t.sub.0 + gt (gate time)                                             t.sub.2 = t.sub.1 + gt                                                          ##STR2##                                                                 

As will be understood from Table 1c, where the input of the first NAND gate N₁ is connected to NAND gate N_(2m-1) in an odd number position, no pulses are formed at the respective output terminals of the NAND gates.

The instant invention will now be described more particularly with reference to the accompanying drawings which show by way of example preferred embodiments of the invention. Referring to the block diagram of FIG. 1d showing a transmission pulse generator employed in the present invention, there are designated at N₁ to N₁₆ a number of NAND gates which are connected in series and which are preferably provided in the form of an integrated circuit. Indicated at C is a terminal for a binary state control signal, which is connected to one of the input terminals of NAND gates N₄ and N₁₁ which have interposed therebetween an even number of similar NAND gates N₅ to N₁₀. The input terminal of the NAND gate N₁ of the first stage is grounded and an output is taken out from the output terminal of NAND gate N₁₆ of the last stage. Each NAND gate has a plural number of input terminals, but those NAND gates which receive input signals by way of a single input terminal, like NAND gates N₁, N₂ and the like, have their input terminals connected to each other to operate as an inverter.

In the pulse waveform generator of FIG. 1d, the outputs of the respective NAND gates undergo level changes as shown in Table 1d below, wherein the character A indicates an initial state where a signal "1" has been applied to the control signal terminal C while B indicates a final state of each output after the control signal is changed to "0" at time t₀.

                                      TABLE 1d                                     __________________________________________________________________________     1○                                                                          2○                                                                        3○                                                                        4○                                                                        5○                                                                        6○                                                                        7○                                                                        8○                                                                        9○                                                                        10○                                                                       11○                                                                       12○                                                                       13○                                                                       14○                                                                       15○                                                                       16○                                                                       17○                                   __________________________________________________________________________     A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ←Initial                                                                   state                                     t.sub.0                                                                          0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0                                            t.sub.1                                                                          0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0                                            t.sub.2                                                                          0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0                                            t.sub.3                                                                          0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0                                            t.sub.4                                                                          0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0                                            t.sub.5                                                                          0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 0                                            t.sub.6                                                                          0 1 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0                                            t.sub.7                                                                          0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0                                            B 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 ←Normal                                                                    state                                     __________________________________________________________________________         : Error state                                                         

More particularly, in the state A, the gate N₁ which has an input "0" produces an output "1" at the terminal 2, the gate N₂ which has an input "1" produces an output "0" at the terminal 3, the gate N₃ which has an input "0" produces an output "1" at the terminal 4, and the gate N₄ which has inputs "1" and "1" produces an output "0" at its terminal 5. In a similar manner, the other NAND gates N₅ to N₁₆ produce outputs of "1" and "0" as indicated to the right of "State A" in Table 1d above. When the input on the control signal terminal C is changed to "0" at time t₀ and after lapse of the time t₁ to t₇, the respective NAND gates finally produce outputs "1" and "0" as shown to the right of "State B" in Table 1d. When the control signal, on the other hand, is changed from "0" to "1," the respective output terminals undergo transitive or transitional states as indicated from t₀ to t₁₂ in Table 2 below before they assume the final state A. The state t₁₃ is same as the final state A. As mentioned hereinbefore, a change in an input signal of a NAND gate produces a change in its output only after a lapse of the so-called gate time, due to the propagation delay which is usually in the order of 6 to 7 nano-seconds. The change in the control signal to the NAND gates N₄ and N₁₁ is transferred to a NAND gate of a succeeding stage after lapse of the gate time, establishing the varying states of the output as shown from t = 1 to 7 of Table 1d and t = 1 to 13 of Table 2.

                                      TABLE 2                                      __________________________________________________________________________     1○                                                                           2○                                                                        3○                                                                        4○                                                                        5○                                                                        6○                                                                        7○                                                                        8○                                                                        9○                                                                        10○                                                                        11○                                                                        12○                                                                        13○                                                                        14○                                                                        15○                                                                        16○                                                                        17○                           __________________________________________________________________________     B  0 1 0 1 1 0 1 0 1 0  1  1  0  1  0  1  0                                    t.sub.0                                                                           0 1 0 1 1 0 1 0 1 0  1  1  0  1  0  1  0                                    t.sub.1                                                                           0 1 0 1 0 0 1 0 1 0  1  0  0  1  0  1  0                                    t.sub.2                                                                           0 1 0 1 0 1 1 0 1 0  1  0  1  1  0  1  0                                    t.sub.3                                                                           0 1 0 1 0 1 0 0 1 0  1  0  1  0  0  1  0                                    t.sub.4                                                                           0 1 0 1 0 1 0 1 1 0  1  0  1  0  1  1  0                                    t.sub.5                                                                           0 1 0 1 0 1 0 1 0 0  1  0  1  0  1  0  0                                    t.sub.6                                                                           0 1 0 1 0 1 0 1 0 1  1  0  1  0  1  0  1                                    t.sub.7                                                                           0 1 0 1 0 1 0 1 0 1  0  0  1  0  1  0  1                                    t.sub.8                                                                           0 1 0 1 0 1 0 1 0 1  0  1  1  0  1  0  1                                    t.sub.9                                                                           0 1 0 1 0 1 0 1 0 1  0  1  0  0  1  0  1                                    t.sub.10                                                                          0 1 0 1 0 1 0 1 0 1  0  1  0  1  1  0  1                                    t.sub.11                                                                          0 1 0 1 0 1 0 1 0 1  0  1  0  1  0  0  1                                    t.sub.12                                                                          0 1 0 1 0 1 0 1 0 1  0  1  0  1  0  1  1                                    t.sub.13                                                                          0 1 0 1 0 1 0 1 0 1  0  1  0  1  0  1  0                                    A  0 1 0 1 0 1 0 1 0 1  0  1  0  1  0  1  0                                    __________________________________________________________________________         : Pulse                                                               

As shown in Table 2, the output appearing at the output terminal 17 of the NAND gate N₁₆ of the last stage assumes a "1" state after the lapse of 6 gate times and, maintains this state for 7 gate times, when the output again assumes a "0" state. Thus, the output of the NAND gate N₁₆ is obtained in the form of a pulse having a width corresponding to 7 gate times. Pulses of a similar width can also be obtained from NAND gates N₁₄ and N₁₂. On the other hand, NAND gates N₁₅, N₁₃ and N₁₁ produce negative pulses of a similar width, which negative pulses have different rise time points which are separated from each other by gate times depending upon the positions of the NAND gates. It will be understood from Table 1d that, when the signal to the control signal terminal C changes from "1" to "0," no pulse output appears at the terminal 17.

The output pulse width can be varied simply by varying the number (even number) of the interposed NAND gates. For example, if the control signal is fed to NAND gates N₄ and N₉ or to NAND gates N₄ and N₇, there will be obtained an output pulse having a width of 5 gate times or 3 gate times respectively. On the other hand, the pulse width becomes larger if an increased number of NAND gates are interposed between the two NAND gates which are connected to the control signal terminal C, the width corresponding to the gate time multiplied by an odd number. In the particular example shown, the width modulation of the pulse is performed only by the NAND gates N₄ to N₁₁ and the other NAND gates do not contribute to the generation of the width-modulated pulses.

The states t₀ to t₇ of Table 1d shows transitive changes which occur when the control signal is changed from "1" to "0." However, in certain cases, the circuit arrangement of FIG. 1d is inconvenient as it takes too much time.

The arrangement of FIG. 2 overcomes this inconvenience, by feeding the control signal to every second NAND gate, more particularly, to NAND gates N₆, N₈ and N₁₀ simultaneously with gates N₄ and N₁₁. With this arrangement, it takes only 2 gate times to attain the state B, as shown in Table 3 below.

                                      TABLE 3                                      __________________________________________________________________________     1○                                                                          2○                                                                        3○                                                                        4○                                                                        5○                                                                        6○                                                                        7○                                                                        8○                                                                        9○                                                                        10○                                                                        11○                                                                        12○                                                                        13○                                                                        14○                                                                        15○                                                                        16○                                                                        17○                            __________________________________________________________________________     A 0 1 0 1 0 1 0 1 0 1  0  1  0  1  0  1  0                                     t.sub.0                                                                          0 1 0 1 0 1 0 1 0 1  0  1  0  1  0  1  0                                     t.sub.1                                                                          0 1 0 1 1 1 1 1 1 1  1  1  0  1  0  1  0                                     t.sub.2                                                                          0 1 0 1 1 0 1 0 1 0  1  1  0  1  0  1  0                                     B 0 1 0 1 1 0 1 0 1 0  1  1  0  1  0  1  0                                     __________________________________________________________________________

When the control signal is changed from "0" to "1," there occur no changes in the outputs of the NAND gates N₆, N₈ and N₁₀ which are fed with the control signal, as shown in FIG. 2, nor in the manner of signal propagation shown in Table 2.

With the circuit arrangement, it is possible to obtain pulses with a width corresponding to an odd multiple of the gate time of the NAND gates which are provided in the form of an integrated circuit. There is sometimes a slight difference in gate time between the individual gates but such difference may be corrected by adjusting the potential of the power supply.

FIG. 3 shows by way of a block diagram a data transmitter according to the invention, using the pulse generator as described hereinabove, where a series of NAND gates N₁₁ to N₁₈ constitute a pulse generator which produces pulses P₇ with a width of 7 gate times, according to the principles discussed hereinbefore. Similarly, a series of NAND gates N₂₁ to N₂₆ constitute a pulse generator which produces pulses P₅ with a width of 5 gate times and a series of NAND gates N₃₁ to N₃₄ constitute a pulse generator which produces pulses P₃ with a width of 3 gate times. The pulse P₇ is used as a start signal and is produced upon application of a control signal C₁. While, the pulses P₃ and P₅ are used as binary data signals "0" and "1," respectively, and are produced by control signals C₂ and C₃ which are generated in accordance with data D₁ to D_(n) set in a number of flip-flop circuits F₁ through F_(n). The NAND gates N₄₁ to N₄₃ produce pulses when the respective pulse generators are in transitive states for triggering the flip-flop circuits F₁ to F_(n) through NAND gates N₄₄ and N₅₁. The three input terminals of the NAND gate N₆₀ are connected to NAND gates N₁₈, N₂₆ and N₃₄ forming the final stages of the respective pulse generators, while its output terminal is connected to an input terminal of an amplifier TA which is connected to a transmission line TL.

The data transmitting operation of the transmitter shown in FIG. 3 is as follows. Upon application of a start signal C₁, the series of NAND gates N₁₁ through N₁₈ produce a pulse P₇ of a 7 gate time width which is fed to a video amplifier TA through NAND gate N₆₀ and, after amplification thereat, is sent onto the transmission line TL. On the other hand, the binary state data D₁ to D_(n) are set beforehand in the flip-flop circuits F₁ through F_(n) which are triggered by the output of NAND gate N₄₁ which detects passage of the start signal S₇ as soon as the latter is transmitted, the output of the NAND gates N₄₁ being passed through NAND gate N₄₄ and N₅₁. The flip-flop circuits F₁ to F_(n) which are adapted to act as a shift register shift data through one gate and the flip-flop circuit F_(n) of the last stage transmits the data. If "0," the data is passed through NAND gate N₅₃ and, if "1," through NAND gate N₅₂ and appear as signal C₂ or C₃ for respectively triggering the NAND gate series N₃₁ to N₃₄ or series N₂₁ to N₂₆. Thus, there will be produced a pulse P₃ for the data signal "0" and a pulse P₅ for the data signal "1," for transmission through NAND gate N₆₀, amplifier TA and transmission line TL. When one bit of data is transmitted, the output of the NAND gate N₄₃ or N₄₂ is passed through the NAND gates N₄₄ and N₅₁ to shift the flip-flop circuits F₁ through F_(n) by one gate. As a result, the next and succeeding data "1" or "0" are transmitted sequentially by repeating the above operations. When all the data which has been set in the flip-flop circuits F₁ to F_(n) is transmitted, all the flip-flop elements assume a "0" state and a stop signal C₄ is fed to the NAND gate N₅₁ to stop the transmission.

In the transmitter of FIG. 3, the respective pulse generators are similarly formed from series of NAND gates N₁₁ to N₁₈, N₂₁ to N₂₆ and N₃₁ to N₃₄ and, since only one of them is required to be operative at one time, they can be arranged into one series as in the transmitter shown in FIG. 4. The transmitter of FIG. 4 operates in a manner similar to the embodiment shown in FIG. 3 and involves pulses of the waveforms as shown in FIG. 5.

In order to transmit data using of the transmitter circuit arrangement of FIG. 4, the data designated by reference characters D₁ through D_(n) are loaded in a suitable number of flip-flop circuits F₁ through F_(n). Before starting the transmission, the signal of FIG. 4 is maintained at a low level (or 0 volt, which will be hereinafter referred to simply as L for brevity), and therefore the NAND gate N₄₄ has an L output while the NAND gates N₅₂ and N₅₃ have an output of a high level (or of 5 volts, which will be hereinafter referred to simply as H for brevity). The transmission is started by changing the signal C₁ from L to H. The series of NAND gates N₁₁ through N₁₈ of FIG. 4 corresponds to the series of NAND gates N₁₁ through N₁₈ of FIG. 3. The level change from L to H of the signal C₁ induces pulses of the waveforms as shown in FIG. 5 in various points of the circuit, generating a pulse of a width of 7 gate times at the output terminal 6 of the NAND gate N₁₉ of FIG. 4. As will be seen from the waveform diagram of FIG. 5, the output 4 of FIG. 4 undergoes a level change to H 2 gate times after a time point when C₁ is changed from L to H, which time point will be hereinlater referred to as a starting point for the convenience of explanation. The output 4 is combined with the output 6 to produce an output 7. Since the output 6 is changed to L 9 gate times after the starting point, the output at the output terminal 7 of the NAND gate N₄₄ is maintained at H for a period of 3 gate times. The output 7 serves to change to L the output of the NAND gate N₅₂ or N₅₃ depending upon the state of the output or the inverted output of the final stage F_(n) of the shift register which is constituted by a number of flip-flop circuits. The output of N₅₂ or N₅₃ forms a pulse of a width of 5 gate times or of 3 gate times from the series of NAND gates N₁₃ to N₁₈ or the series of NAND gates N₁₅ to N₁₈.

In the timing chart shown by way of example in FIG. 5, the data D_(n) which is to be transmitted is a "1." The series of NAND gates N₁₃ to N₁₈ undergoes changes in state to change the output from H to L, producing a pulse of 5 gate time width. This appears at the output terminal 6 at a time point 14 gate times after the starting point. Since the waveform propagate through the series of NAND gates N₁₃ to N₁₈, the potential at 4 is changed from L to H by the propagation, triggering the transmission of the next data through 7. An output which is an invertion of the output 7 appears at 12 and serves to shift the shift register which is formed from a group of flip-flop circuits F₁ through F_(n).

FIG. 6 is a circuit diagram of a receiver, where the reference characters n₁ through n₁₁ show a series of NAND gates which are also provided in the form of integrated circuits. The first stage of the NAND gates series n₁ to n₁₁ receives a width-modulated pulse through a transmission line TL and an amplifier RA. The reference characters n₁₂ through n₁₈ also designate NAND gates, of which n₁₂ is connected to NAND gates n₅, n₈ and n₁₁, n₁₃ is connected to NAND gates n₃, n₆, n₈ and n₁₁, and n₁₄ is connected to NAND gates n₁, n₄, n₈ and n₁₁ for receiving outputs 6, 9 and 12, outputs 4, 7, 9 and 12 and outputs 2, 5, 9 and 12, respectively. The NAND gates n₁₅ and n₁₆ are respectively connected to NAND gates n₁₂ and n₁₃ and at the same time to each other to form a latching circuit. The NAND gate n₁₂ produces a pulse of a 3 gate time width upon receipt of a 3 gate time pulse P₃, while the NAND gate n₁₃ produces a pulse of a 3 gate time with upon receipt of a 5 gate time pulse P₅. The NAND gate n₁₈ is connected to the NAND gates n₁₂ and n₁₃ and produces a synchronizing signal C "1" (of a width of three gate times). On the other hand, the NAND gate n₁₄ produces a pulse of a three gate time width upon receipt of a seven gate time pulse P₇. This receiver circuit operates in the manner as follows.

If an input pulse of the three gate time pulse P₃ is received at the input terminal 1 of the first step n₁ of the NAND gate series n₁ through n₁₁, the respective NAND gates outputs 2 through 12 as well as O₃, O₅ and O₇ undergo changes as shown in Table 4 below, where t = 1 shows the instant when the input pulse is imposed, and t = 2 and t = 3 show the time points after lapses of one gate time and two gate times, respectively.

                                      TABLE 4                                      __________________________________________________________________________     t  1○                                                                        2○                                                                        3○                                                                        4○                                                                        5○                                                                        6○                                                                        7○                                                                        8○                                                                        9○                                                                        10○                                                                        11○                                                                        12○                                                                        O.sub.3                                                                           O.sub.5                                                                           O.sub.7                                    __________________________________________________________________________     t.sub.0                                                                           0 1 0 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.1                                                                           1 1 0 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.2                                                                           1 0 0 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.3                                                                           1 0 1 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.4                                                                           0 0 1 0 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.5                                                                           0 1 1 0 1 1 0 1 0 1  0  1  1  1  1                                          t.sub.6                                                                           0 1 0 0 1 0 0 1 0 1  0  1  1  1  1                                          t.sub.7                                                                           0 1 0 1 1 0 1 1 0 1  0  1  1  1  1                                          t.sub.8                                                                           0 1 0 1 0 0 1 0 0 1  0  1  1  1  1                                          t.sub.9                                                                           0 1 0 1 0 1 1 0 1 1  0  1  1  1  1                                          t.sub.10                                                                          0 1 0 1 0 1 0 0 1 0  0  1  0  0  1                                          t.sub.11                                                                          0 1 0 1 0 1 0 1 1 0  1  1  0  1  1                                          t.sub.12                                                                          0 1 0 1 0 1 0 1 0 0  1  0  0  1  1                                          t.sub.13                                                                          0 1 0 1 0 1 0 1 0 1  1  0  1  1  1                                          t.sub.14                                                                          0 1 0 1 0 1 0 1 0 1  0  0  1  1  1                                          t.sub.15                                                                          0 1 0 1 0 1 0 1 0 1  0  1  1  1  1                                          __________________________________________________________________________      *    : Pulse                                                             

As is clear from Table 4, if a pulse of a three gate time width is received at the input terminal 1, this it appears at the output terminals of the respective NAND gates at a time delay of one gate time from a preceeding one. The outputs at the output terminals 6, 9, 12, output terminals 4, 7, 9 and 12, and output terminals 2, 5, 9 and 12 of the respective NAND gates are pulsed in the same manner as indicated at O₃, O₅ and O₇ of Table 4, only the output O₃ of the NAND gate N₁₂ producing an output of "0" level over a period of three gate times. In other words, when the output of the NAND gate N₁₅ is a = "1," it is possible to know that the received input signal is a three gate time pulse P₃. In this instance, a pulse output of one gate time appears at O₅, however, it decays during propagation through the circuit as it has only a small duration and therefore gives no adverse effects on the ultimate output.

If a five gate time pulse P₅ is received at the input terminal 1 of the receiver of FIG. 6, the outputs 2 through 12 of the NAND gates n₁ through n₁₁ and outputs O₃, O₅ and O₇ of the NAND gates n₁₂ to n₁₄ undergo changes as shown in Table 5 below.

                                      TABLE 5                                      __________________________________________________________________________     t  1○                                                                        2○                                                                        3○                                                                        4○                                                                        5○                                                                        6○                                                                        7○                                                                        8○                                                                        9○                                                                        10○                                                                        11○                                                                        12○                                                                        O.sub.3                                                                           O.sub.5                                                                           O.sub.7                                    __________________________________________________________________________     t.sub.0                                                                           0 1 0 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.1                                                                           1 1 0 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.2                                                                           1 0 0 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.3                                                                           1 0 1 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.4                                                                           1 0 1 0 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.5                                                                           1 0 1 0 1 1 0 1 0 1  0  1  1  1  1                                          t.sub.6                                                                           0 0 1 0 1 0 0 1 0 1  0  1  1  1  1                                          t.sub.7                                                                           0 1 1 0 1 0 1 1 0 1  0  1  1  1  1                                          t.sub.8                                                                           0 1 0 0 1 0 1 0 0 1  0  1  1  1  1                                          t.sub.9                                                                           0 1 0 1 1 0 1 0 1 1  0  1  1  1  1                                          t.sub.10                                                                          0 1 0 1 0 0 1 0 1 0  0  1  1  0  0                                          t.sub.11                                                                          0 1 0 1 0 1 1 0 1 0  1  1  1  0  1                                          t.sub.12                                                                          0 1 0 1 0 1 0 0 1 0  1  0  0  0  1                                          t.sub.13                                                                          0 1 0 1 0 1 0 1 1 0  1  0  1  1  1                                          t.sub.14                                                                          0 1 0 1 0 1 0 1 0 0  1  0  1  1  1                                          t.sub.15                                                                          0 1 0 1 0 1 0 1 0 1  1  0  1  1  1                                          t.sub.16                                                                          0 1 0 1 0 1 0 1 0 1  0  0  1  1  1                                          t.sub.17                                                                          0 1 0 1 0 1 0 1 0 1  0  1  1  1  1                                           *    : pulse                                                             

In this instance, pulses of five gate time width appear at the output terminals of the respective NAND gates n₁ through n₁₁, at a delay of one gate time from a preceeding one. Similar to the operation with the three gate time pulse described hereinbefore, the NAND outputs at n₁₂, n₁₃ and n₁₄ for the outputs 6, 9, 12, outputs 4, 7, 9, 12 and outputs 2, 5, 9, 12 become as shown at O₃, O₅ and O₇ in Table 5, respectively, and only the NAND gate N₁₆ produces an output of "0" level over a period of three gate times. The outputs O₃ and O₇ decay during propagation through the circuit and therefore impose no influences on the ultimate output. Thus, when the output of the NAND gate N₁₆ is b = 1, it is known that the received input signal is the five gate time pulse P₅.

If a seven gate time pulse P₇ is received at the input terminal 1, the outputs of the respective NAND gates undergo changes as shown in Table 6 below.

                                      TABLE 6                                      __________________________________________________________________________     t  1○                                                                        2○                                                                        3○                                                                        4○                                                                        5○                                                                        6○                                                                        7○                                                                        8○                                                                        9○                                                                        10○                                                                        11○                                                                        12○                                                                        O.sub.3                                                                           O.sub.5                                                                           O.sub.7                                    __________________________________________________________________________     t.sub.0                                                                           0 1 0 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.1                                                                           1 1 0 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.2                                                                           1 0 0 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.3                                                                           1 0 1 1 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.4                                                                           1 0 1 0 0 1 0 1 0 1  0  1  1  1  1                                          t.sub.5                                                                           1 0 1 0 1 1 0 1 0 1  0  1  1  1  1                                          t.sub.6                                                                           1 0 1 0 1 0 0 1 0 1  0  1  1  1  1                                          t.sub.7                                                                           1 0 1 0 1 0 1 1 0 1  0  1  1  1  1                                          t.sub.8                                                                           0 0 1 0 1 0 1 0 0 1  0  1  1  1  1                                          t.sub.9                                                                           0 1 1 0 1 0 1 0 1 1  0  1  1  1  1                                          t.sub.10                                                                          0 1 0 0 1 0 1 0 1 0  0  1  1  1  0                                          t.sub.11                                                                          0 1 0 1 1 0 1 0 1 0  1  1  1  1  0                                          t.sub.12                                                                          0 1 0 1 0 0 1 0 1 0  1  0  1  0  0                                          t.sub.13                                                                          0 1 0 1 0 1 1 0 1 0  1  0  1  1  1                                          t.sub.14                                                                          0 1 0 1 0 1 0 0 1 0  1  0  1  1  1                                          t.sub.15                                                                          0 1 0 1 0 1 0 1 1 0  1  0  1  1  1                                          t.sub.16                                                                          0 1 0 1 0 1 0 1 0 0  1  0  1  1  1                                          t.sub.17                                                                          0 1 0 1 0 1 0 1 0 1  1  0  1  1  1                                          t.sub.18                                                                          0 1 0 1 0 1 0 1 0 1  0  0  1  1  1                                          t.sub.19                                                                          0 1 0 1 0 1 0 1 0 1  0  1  1  1  1                                          __________________________________________________________________________      *    * Pulse                                                             

In this instance, it is only the NAND gate N₁₄ that produces an output of "0" level over a period of three gate times, so that, when the output of the NAND gate n₁₇ is d = "1" (3 gate times), it is known that the received input signal is the seven gate time pulse P₇. The output O₅ decays during propagation through the circuit and therefore imposes no influence on the ultimate output. In general, if the output of n₁ is H₂ and the output of n_(n-1) is H_(n), an AND output of H2m, H2m + 3, H2m + 3 + w and H2m + 6 + w (where w is a natural number) forms a three gate time pulse in response to an input pulse having a width w.

It will be appreciated from the foregoing description that the use of a pulse having a width corresponding to a multiple of a gate time or a prepagation delay of IC NAND gates makes it possible to effect the generation and demodulation of pulses in an extremely simplified manner by providing a similar NAND gate group for the transmitter, allowing simplification of both transmitter and receiver circuits to a considerable degree. Furthermore, a single line suffices to effect the transmission since there is no need for the provision of a line for a clock signal, contributing to significant reductions of cabling burdens. Since the data and subsidiary information are transmitted by means of pulses of different widths which correspond to multiples of a unit gate time, it is possible to adopt multi-value logic data and to increase the kinds of subsidiary information, that is to say, to increase the number of symbols in a quite simple manner, in contrast to the known binary code system where it is required to allot to a single symbol a combination of a number of binary codes.

Though a width-modulated pulse is demodulated by the circuit of FIG. 6, the pulse demodulation may be effected also by means of a demodulator having a combination of pulse waveform edge detector and a delay circuit.

FIG. 7 shows an example of a pulse waveform front edge detector, where there is shown at L₁ an input signal line, at DL a delay line, at I₃ and I₄ inverters and at L₂ an output signal line, all connected in series in the order mentioned. Designated at AG is an AND gate which has a pair of input terminals Ga and Gb respectively connected to signal input and output terminals Pa and Pb of the series circuit of the delay line DL and the inverter I₃.

The circuit of FIG. 7 operates as follows. When a rectangular pulse arrives at the input signal line L₁ and reaches the point Pa, the level at Pa becomes "1" (a state where a signal is present) but the node Pc between the delay line DL and the Inverter I₃ remains "0" as the signal has not yet arrived thereat. Therefore, the level at the point Pb is held at "1" by the action of the inverter I₃. Thus, the AND gate AG produces an output "1" after lapse of an internal propagation time tda. When the rectangular pulse is passed to the point Pc through the delay line DL which has a signal propagation delay of td₂, the inverter I₃ produces an output "0" after a time lapse of td₁ while the AND gate AG produces an output "0" after a time lapse of tda. Thus, an output pulse indicating the front edge of the rectangular input pulse is obtained from the AND gate AG, which output pulse appears at a delay of tda after the time point when the input rectangular pulse reaches the point Pa and has a width corresponding to td₂ + td₁ which is a sum of the delays caused by the delay line DL and the inverter I₃. The width of the output pulse can be varied by changing the delay time of the delay line DL, to a width suitable for use in a succeeding circuit.

As the rectangular input pulse further proceeds and its rear edge is passed through the point Pa, the level at the input terminal Ga of the AND gate AG becomes "0". The AND gate AG receives inputs "0," "0" and therefore has no changes in its output "0." Upon the rear edge of the rectangular input pulse passing through the point Pc, the inverter I₃ produces an output "1" after a time lapse of td₁. However, the output of the AND gate AG remains "0" as its inputs are still "0" and "1." Thus, this circuit is insensitive to the rear edge of the input pulse and maintains the same output. In this instance, the inverter I₄ serves to maintain the polarity of the input and output signals unchanged, inverting again the "1" and "0" levels of the rectangular input signal which has been inverted by the inverter I₃ to restore the initial state. Therefore, the inverter I₄ may be eliminated, if unnecessary.

The rear edge of the rectangular input pulse can be detected by adding an inverter. More particularly, the front edge of the rectangular input pulse resides at a point of level change from 37 0" and "1" while the rear edge resides at a point of level change from 37 1" to 38 0," so that the rear edge can be converted into a front edge having a level change from "0" to "1." FIG. 8 shows a rear edge detector employing an inverter I₅ for this purpose. It may be remarked that similar parts are designated by similar reference characters throughout the various figures. The rear edge detector of FIG. 8 operates in a manner similar to the embodiment shown in FIG. 7. Since the detector of FIG. 8 used two inverters, there is no need for employing an additional phase inverter as shown at I₄ in FIG. 7.

With the front and rear edge detectors shown in FIGS. 7 and 8, the detection takes only an extremely short time corresponding to the internal signal propagation time tda of the AND gate which is in the order of several to several tens nano-seconds, so that the data transmission can be effected at an extremely high rate.

FIGS. 9a and 9b show examples of front and rear edge detectors using IC inverters and IC NAND gates, respectively, where I₁, I₂ and I₃ designate inverters, and NG₁ designates a NAND gate. These detector circuits have the inverters I₁ and I₂ connected in series to serve as a delay element which corresponds to the delay line DL of FIGS. 7 and 8. According to experiments, all the inverters (SN 7404, SN 7400, products of Texas Instruments, Inc.) had an internal delay time of about 6 nano-seconds. Therefore, the combination of the inverters I₁ and I₂ operates as a delay element of about 12 nano-seconds. Potentials at the input terminal of the inverter I₁ and the output terminal of the inverter I₃ are connected to the NAND gate NG₁ to produce an AND output inverted in phase. In the particular example shown, the NAND gate NG₁ has an internal delay time of about 6 nano-seconds.

The front and rear edge detectors just described can carry out the detection and demodulation of width-modulated pulses in a facilitated manner and can find a variety of applications.

FIG. 10 shows an example of an application of the front and rear edge detectors, which are used in a pulse width detector for detecting a pulse of a predetermined width among a number of input pulses of different widths and where FD indicates a front edge detector as shown in FIG. 7, TD indicates a rear edge detector as shown in FIG. 8, DLo indicates a delay element having a signal propagation delay time of td₃ according to a pulse width to be detected, and AGo indicates an AND gate.

In this pulse width detector circuit arrangement, the front edge of a rectangular pulse received at the input terminal is passed through the delay line DLo and allowed to enter the front edge detector FD after a time lapse of td₃ and appears at its output terminal after a further time lapse of tda as a pulse having a width corresponding to (td₁ + td₂). On the other hand, the rear edge of the rectangular pulse received at the input terminal of the detector, if the pulse has a width of tdx, enters the rear edge detector TD after a time lapse of tdx and appears at its output terminal after a further time lapse of td₁ + tda as a pulse having a width corresponding to (td₁ + td₂). Since the AND gate AGo produces a "1" output only when it receives input pulses simultaneously from the detectors FD and TD, the output comes from the AND gate AGo when td₃ + tda = tdx + td₁ + tda. Namely, if the delay line DLo has a delay time of td₃ = tdx + td₁ ≈ tdx, it is possible to detect a pulse having a width corresponding to the delay time of the line DLo upon arrival thereof. As the output pulses of the front and rear edge detectors FD and TD have a width of td₁ + td₂, the AND gate produces a detection output even if there is a slight time deviation between the two outputs.

When the output pulses of the front and rear edge detectors FD and TD have a width of tdo (= td₁ + td₂), the output pulse of the AND gate AGo has a width ta as shown in FIG. 11. More particularly, when the width tdx of the rectangular input pulse and the delay time td₃ of the delay element DLo coincide with each other, the output pulses of the front and rear edge detectors FD and TD are perfectly superimposed one on the other and the output pulse of the AND gate AG has a width ta of a maximum value. The pulse width ta becomes smaller with a larger difference between tdx and td₃ and becomes zero when |tdx - td₃ | ≧ tdo. As a result, when pulses of different widths are received by the input terminal, the circuit detects those pulses which have a width corresponding to the delay time of the delay line DLo and produces output pulses having a width ta as shown particularly in FIG. 11.

In this instance, it should be noted that, in detecting the signals, the detector of the invention does not require synchronizing signals as used in known data transmission systems, or control of auxiliary signals including reproduction of synchronizing signal after reception thereof, or the like. Therefore, the invention is completely free from such difficulties as experienced in existing counterparts, including phase shifts or synchronizing signals or complication of circuit design due to necessity for the provision of a circuit for the reproduction of synchronizing signals. This can be a great advantage in designing the transmission passage.

FIG. 12 shows an example which utilizes the afore-mentioned pulse width detection circuit for demodulation of width-modulated pulses, where indicated at d₀, d₁, d₂ and d₃ are delay elements having a delay time of t₀, t₁, t₂ and t₃, respectively, at FD is a front edge detector circuit, at TD₁, TD₂ and TD₃ are rear edge detector circuit, and at A₁, A₂ and A₃ are AND gates. The delay times t₀, t₁, t₂ and t₃ are selected such that they become gradually shorter from t₁ to t₃. Only four delay elements are shown in FIG. 12, however, more can be arranged in a manner similar to d₁, TD₁ and A₁ or d₂, TD₂ and A₂.

The circuit of FIG. 12 operates as follows. If a rectangular pulse arrives at the input terminal, the front edge detector circuit FD produces a detection output pulse after a time lapse of t₀ and this is fed to the input terminals of the AND gates A₁, A₂ and A₃. After the rear edge of the rectangular input pulse has passed through the input terminal, the rear edge detector circuits TD₁, TD₂ and TD₃ produce respective outputs with time lapses of t₁, t₂ and t₃, respectively. More particularly, if the rectangular input pulse has a width tw and the delay element which is connected to the rear edge detector has a delay time tx, and AND gate produces an output when t₀ = tw + tx. Thus, an output is produced only from the AND gate which is connected to a rear edge detector with a delay element having a delay time tx. The pulse demodulation can be carried out suitably by presetting t.sub. 1 + t₂ and t₃ in accordance with the widths of the rectangular input pulses.

FIG. 13 shows a modification of the demodulator of FIG. 12, which is also adapted to demodulate width-modulated pulses. In the demodulator circuit arrangement of FIG. 13, when a front edge of a rectangular pulse of a certain width reaches the front edge detector circuit FD, the rear edge detector circuits TD₁ through TD_(n) watch the rear end of the pulse and, after passage of the rear edge, an AND gate, for example, the AND gate A₂ which is connected to TD₂ produces an output, thus demodulating a width-modulated pulse. Of course, the delay times of the delay elements d₁ through d_(n) are preset according to the widths of pulses to be demodulated.

The width-modulated pulse demodulator circuits of FIGS. 10, 12 and 13 are all adapted to produce an output only in response to reception of rectangular pulses having a variety of predetermined widths. These circuits detect reception of pulses other than of the predetermined widths but produce no outputs in response thereto. This applies to a case where an output appears only at the front edge detector FD or only at the rear edge detector TD. That is to say, it occurs when noises are produced in the communication passage. Thus, the detectors have functions to discriminate noises generated and such functions can be a great advantage in the treatment of noises in general.

FIG. 14 is a circuit diagram of a receiver employing the width-modulated pulse demodulator according to the invention, where DL₁ and DL₂ indicate delay lines corresponding to the element d₀ of FIG. 12 and DL₃ and DL₄ indicate delay elements similarly corresponding to the elements d₁ and d₂, respectively. The example shown in FIG. 14 utilizes the fact that there occurs no change in the function of the detector circuits even if a value corresponding to d₃ is removed from the respective delay elements, as in FIG. 12 where no change occurs even if the respective delay times d₀, d₁, d₂ and d₃ are altered by a set value. In FIG. 14, Ii (i = 11 through 27) indicates inverters which are provided in the form of an integrated circuit. Inverters I₁₂, I₁₃, I₁₄ and I₁₅ constitute together with a NAND circuit NG₁ a front edge detector circuit which corresponds to FD of FIG. 12, while the group I₁₇, I₁₈ and I₁₉, group I₂₁, I₂₂ and I₂₃ and group I₂₅, I₂₆ and I₂₇ constitute, together with NAND circuits NG₁ to NG₃ , rear edge detector circuits which correspond to TD₁, TD₂ and TD₃ of FIG. 12, respectively. The inverters of the group including I₁₃ and I₁₄, the group including I₁₇ and I₁₈, the group including I₂₁ and I₂₂ and the group including I₂₅ and I₂₆ are all connected in series to act as a delay element for imparting a suitable width to the edge detection output pulse. These inverter groups correspond to the delay line DL of FIGS. 7 and 8. In the circuit arrangement of FIG. 14, a signal undergoes phase inversion through inverters I₁₁, I₁₆, I₂₀ and I₂₄, so that the front and rear edge detectors have inverted circuit arrangements as compared with those of FIGS. 7 and 8. The NAND circuits NG₁ to NG₃ of FIG. 14 correspond to AND circuits A₁ to A₃ of FIG. 12, repsectively. NG₆ and NG₇ have no counterparts in the embodiment of FIG. 12 but they constitute a flip-flop circuit for retaining data. The NAND circuits NG₈, NG₉ and NG₁₀ constitute a synchronizing pulse generator for the control of a shift register which is connected to the last stage. The outputs of the NAND circuits NG₅ and NG₈ are used for detecting the arrival of a noise waveform by means of a detector Err.

The waveforms (a), (b) and (c) of FIG. 15 are of the three pulses which are detected by the width-modulated pulse demodulator of FIG. 14. These pulse waveforms correspond to three items of information namely "1," "0" and "STX," respectively. Other pulse waveforms are detected as noises by the detector Err.

FIG. 16 shows an example of a pulse generator circuit for producing waveforms as shown in FIG. 15, where N₁₁₁ to N₁₁₈, N₁₂₀ to N₁₂₈ and N₁₃₀ to N₁₃₈ indicate NAND gates, respectively, TM₁ indicates an input terminal for a start signal, TM₂ indicates an input terminal for the data "1" and "0," TM₃ indicates an output terminal for a width-modulated pulse, and TM₄ indicates an output terminal for a data cycle pulse. This pulse generator circuit operates in the manner as already described hereinbefore with reference to FIGS. 3 and 4. In brief, when TM₁ is at the L level, the circuit is in a stop state. Under these circumstances, no waveform can propagate through the series of NAND gates N₁₁₁ to N₁₁₈, holding the output of N₁₃₀ at L level and the outputs of N₁₃₁ and N₁₃₂ at H level. Since the ouput of N₁₃₃ is at the L level, no waveform propagates through the series of NAND gates N₁₂₀ to N₁₂₈. When the potential at TM₁ is changed to the H level, a pulse having a 7 gate time width is produced through N₁₁₈ for the reasons as explained hereinbefore in connection with FIGS. 1 and 2. With a time lapse of 8 gate times after the level change of TM₁ to H, the output of N₁₃₀ changes from L to H level. Since the outputs of N₁₂₂ and N₁₂₅ are at the H level, the outputs of N₁₃₁ and N₁₃₂ change to the L level. The process after this varies depending upon whether TM₂ is at the H level or at the L level. In the case where TM₂ is at the H level, the input terminals A to G, except for the input terminal C of the NAND gate N₁₂₃, are all at the L level before the afore-mentioned outputs of N₁₃₁ and N₁₃₂ change from H to L level. When the ouputs of N₁₃₁ and N₁₃₂ change from H to L level, the input terminals A to G and TM₄ change from L to H level, except for the input terminal C. At this time, the NAND gates which are connected to E, F and G act as a pulse generator circuit as described in connection with FIG. 1 or 2, producing a pulse with a 3 gate time width. With a time lapse of 2 gate times from the time point when input terminals A, B, D to G and TM₄ change from the L to H level, the output of N₁₃₂ changes to the H level, while N₁₃₁ changes to the H level after a time lapse of 4 gate times. p The operation then proceeds to the transmission of the next data. When TM₂ is at the L level, the input terminals A to G are likewise at the L level excpet for the terminal D which is at the H level. When the outputs of N₁₃₁ and N₁₃₂ change to the L level, the NAND gate input terminals C, E to G and TM₄ operate as a pulse generator circuit as discussed hereinbefore in connection with FIG. 1 or 2, producing a pulse having a 5 gate time width. N₁₃₁ changes again to the H level with a time lapse of 4 gate times from the time point when A changes from the L to H level, while N₁₃₂ changes similarly to the H level with a time lapse of 4 gate times from the time point when C changes to the H level. Whereupon, the operation proceeds to the next data transmission cycle. By this time, the next data to be transmitted should be provided in a ready state at the input terminal TM₂. This can be attained by connecting the output of TM₄ to the shift register and the output of the shift register to TM₂. In this instance, depending upon whether the prepared data or the input terminal TM₂ is at the H level or the L level, either one of the NAND gate input terminals C and D is selected to assume the L level. N₁₃₂ changes again to the L level with a time lapse of 7 gate times from the previous level change of A from the L to H level, and, with a further time lapse of 1 gate time, causes C or D, A, B, E to G and TM₄ to change from the L to H level, producing through N₁₂₈ a pulse having a width corresponding to the input data. Thus, the transmission of a width-modulated pulse for the succeeding data is effected at a time interval of 5 gate times when the preceeding pulse has a width of 3 gate times and at a time interval of 3 gate times when the preceeding pulse has a width of 5 gate times. This depends on which one of the series of NAND gates, N₁₂₀ to N₁₂₄ or LN₁₂₀ to N₁₂₂, is used, that is to say, upon the number of the gates involved. The pulse waveforms of FIG. 15 each has a width corresponding to a multiple by an odd number of 6 nano-seconds.

Of the waveforms of FIG. 15, the waveform (c) which has a width of 42 nano-seconds corresponds to an alphabet "STX," which is detected by the front edge detector of FIG. 14 including inverters I₁₃ to I₁₅ and also by the rear edge detector including inverters I₂₅, to I₂₇, to produce an output O_(STX) at the NAND circuit NG₃. In order to get the front edge of the signal waveform (c) to appear on the output of the inverter I₁₂ simultaneously with appearance of the rear edge on the output of the inverter I₂₄, there should be a time difference of 42 nano-seconds between these two outputs. Where the inverter I₁₁, has an internal propagation delay of 6 nano-seconds, the delay line constituted by DL₁ and DL₂ is required to give a delay of 36 nano-seconds. After setting the delay time for the signal waveform of the largest width, the delay times of DL₄ and DL₃ are set at 12 nano-seconds and 24 nano-seconds, respectively, for the detection of the signal waveform of 30 nano-seconds (alphabet "0") and the signal waveform of 18 nano-seconds (alphabet "1"), the respective outputs due to arrival of a pulse appearing at the NAND circuits NG₂ and NG₁. Each of these outputs is in the form of an instantaneous pulse and stored in the flip-flop circuit which is constituted by NAND gates NG₆ and NG₇, to give an output O_(D). The output appearing either at the NAND circuit NG₁ or NG₂ is simultaneously subjected to OR operation in the NAND circuit NG₈, which can be utilized as a synchronizing signal O_(SYN). The "STX" output O_(STX) appearing at the NAND circuit NG₃ serves to denote a punctuation point between the individual message (formed from two alphabets of "1" and "0").

As disclosed hereinabove, the receiver circuit of the invention is adapted to produce an output only in response to a pulse of a particular width, in a manner to allow facilitated digital transmission according to the pulse width modulation. This receiver circuit, furthermore, has a desirable property of promptly detecting the occurrence of noises, thus being effective in enhancing the promptness of counteraction against noises and improving the quality of data transmission lines. The receiver circuit, moreover, may be constructed by the use of integrated circuits. This facilitates suitable coordination of the speed of the receiver operation with that of electronic computer circuits which also comprise ICs, making the receiver suitable for use in high speed data transmission apparatus.

By combining wave edge detecting circuits and delay circuits, a pulse train of a particular waveform which train is suitable for use in various codes may easily be detected. Referring to FIG. 17 showing one example of a pulse train to be detected, the train comprises three pulses S₁, S₂ and S₃, respectively having a width of tw₁, tw₂ and tw₃. The three pulses are aligned in series, interspaced by time intervals t'w₁ and t'w₂. The pulse train comprising the three pulses thus conveys information.

Referring to FIG. 18 showing a receiver circuit, d₁, d₂, d₃, d₄ and d₅ denote delay elements respectively having signal propagation delay time t₁, t₂, t₃, t₄ and t₅, which delay time respectively correspond to pulse widths and pulse intervals tw₁, t'w₁, tw₂, t'w₂ and tw₃. F₁, F₂, F₃ denote pulse front edge detection circuits and T₁, T₂, T₃ denote pulse rear edge detection circuits while AGo is an AND gate which is adapted to receive outputs from said detection circuits F₁ - F₃ and T₁ - T₃. Delay lines may be suitably employed as the delay element d₁ - d₅. Also, a plurality of IC inverters connected in series, said inverters having suitable signal propagation delay time, may well be used as the delay elements.

Operation of the receiver circuit is now described with reference to the drawings. A pulse train as shown in FIG. 17 enters the receiver circuit at a signal input terminal. When a front edge and a rear edge of each pulse S₁ to S₃ pass through front edge detecting circuits F₃ to F₂, and rear edge detecting circuts T₃ to T₂ successively, each detecting circuit generates a pulse of a predetermined width as a result of detection. In this case, however, signals applied to the AND gate AGo are at the "1" level partially (assuming the "1" level to be the case where the front edge and the rear dge detecting circuits produce outputs) and a pulse train is not generated. When the front edge of the pulse S₁ is detected by the pulse front edge detection circuit, however, the rear edge of the pulse S₁ is detected by the rear edge detection circuit T₁. Similarly, the front and the rear edges of the pulse S₂ are detected by the front and the rear edge detection circuits F₂ and T₂, and the front and the rear edges of the pulse S₃ are detected by the front and the rear edge detection circuits F₃ and T₃, with a result that all the input signals applied to the AND gate AGo are at the "1" level, causing the gate to generate a pulse train. When a pulse having a wave form other than the pulse train shown in FIG. 17 is applied to the input terminal, one or more of the detection circuits F₁ to F₃ and T₁ and T₃ fail to generate an output, and accordingly the AND gate AGo does not generate an output. In this manner, the receiver circuit shown in FIG. 18 discriminately detects a pulse signal of a particular waveform from various pulses applied to the input terminal.

In order to detect a pulse train having a waveform other than that shown in FIG. 17, the number of delay elements, pulse front edge and rear edge detectors as well as the delay time for the delay elements are adjusted in accordance with a number of pulses, pulse widths and pulse intervals constituting the particular pulse train to be detected.

The present invention has been disclosed in detail hereinabove with reference to preferred embodiments. Needless to say, the application of the present invention is in no way restricted to the particular embodiments illustrated susceptible to various changes and modifications or alterations within the scope of the invention as defined in the appended claims. 

What is claimed is:
 1. A width-modulated pulse demodulator system for receiving pulses of different widths and decoding them, said demodulator system comprising a plurality of delay elements each having a different delay time, each of said delay elements receiving said pulses of different widths, a front-edge-waveform detector circuit serially connected to the output of the delay element having the longest delay time, a plurality of rear-edge-waveform detector circuits each serially coupled to a respective one of the remaining delay elements, and a plurality of AND gates each having two inputs, one input of each AND gate being commonly connected to the output of said front-edge-waveform detector circuit, and the other input of each AND gate connected to a respective output of said rear-edge-waveform detector circuits.
 2. The system of claim 1 and wherein said front-edge-waveform detector comprises delay means, an inverter in series with said delay means, and an AND gate having two input terminals, one of which is connected to the input of said delay means and the other of which is connected the the output of said inverter.
 3. The system of claim 2 and wherein said delay means and said inverter are formed of NAND gates in the form of an integrated circuit.
 4. The system of claim 1 and wherein said rear-edge-waveform detector comprises in series combination, a first inverter, a delay means and a second inverter, and further includes an AND gate having two input terminals, one of which is connected to the input to said delay means and the other of which is connected to the output of said second inverter.
 5. The system of claim 4 and wherein said delay means and said first and second inverters are formed of NAND gates in the form of an integrated circuit.
 6. A width-modulated system for receiving pulses of different widths and decoding them, said demodulation system comprising a plurality of delay elements and a corresponding plurality of rear-edge-waveform detector circuits alternately connected in series circuit arrangement with said delay elements, said circuit arrangement commencing with a rear-edge-waveform detector circuit which receives said pulses of different widths, and said circuit arrangement terminating with a delay element, a front-edge-waveform detector circuit serially coupled to said terminating delay element, and a corresponding plurality of AND gates each having two inputs, one input of each AND gate being commonly connected to the output of said front-edge-waveform detector circuit, and the other input of each AND gate connected to a respective output of said rear-edge-waveform detector circuits.
 7. The system of claim 6 and wherein said front-edge-waveform detector comprises delay means, an inverter in series with said delay means, and an AND gate having two input terminals, one of which is connected to the input of said delay means and the other of which is connected to the output of said inverter.
 8. The system of claim 7 and wherein said delay means and said inverter are formed of NAND gates in the form of an integrated circuit.
 9. The system of claim 8 and wherein said rear-edge-waveform detector comprises in series combination, a first inverter, a delay means and a second inverter and further includes an AND gate having two input terminals, one of which is connected to the input to said delay means and the other of which is connected to the output of said second inverter.
 10. The system of claim 4 and wherein said delay means and said first and second inverters are formed of NAND gates in the form of an integrated circuit. 